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12-42. STEPDELAY10 Register .............................................................................................. 1076
12-43. STEPCONFIG11 Register............................................................................................. 1077
12-44. STEPDELAY11 Register .............................................................................................. 1078
12-45. STEPCONFIG12 Register............................................................................................. 1079
12-46. STEPDELAY12 Register .............................................................................................. 1080
12-47. STEPCONFIG13 Register............................................................................................. 1081
12-48. STEPDELAY13 Register .............................................................................................. 1082
12-49. STEPCONFIG14 Register............................................................................................. 1083
12-50. STEPDELAY14 Register .............................................................................................. 1084
12-51. STEPCONFIG15 Register............................................................................................. 1085
12-52. STEPDELAY15 Register .............................................................................................. 1086
12-53. STEPCONFIG16 Register............................................................................................. 1087
12-54. STEPDELAY16 Register .............................................................................................. 1088
12-55. FIFO0COUNT Register................................................................................................ 1089
12-56. FIFO0THRESHOLD Register......................................................................................... 1090
12-57. DMA0REQ Register.................................................................................................... 1091
12-58. FIFO1COUNT Register................................................................................................ 1092
12-59. FIFO1THRESHOLD Register......................................................................................... 1093
12-60. DMA1REQ Register.................................................................................................... 1094
12-61. FIFO0DATA Register .................................................................................................. 1095
12-62. FIFO1DATA Register .................................................................................................. 1096
13-1. LCD Controller .......................................................................................................... 1098
13-2. LCD Controller Integration............................................................................................. 1100
13-3. Input and Output Clocks............................................................................................... 1102
13-4. Logical Data Path for Raster Controller ............................................................................. 1109
13-5. Frame Buffer Structure ................................................................................................ 1110
13-6. 16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 BPP).............................................................. 1111
13-7. 256-Entry Palette/Buffer Format (8 BPP) ........................................................................... 1112
13-8. 16-BPP Data Memory Organization (TFT Mode Only)—Little Endian .......................................... 1112
13-9. 12-BPP Data Memory Organization—Little Endian................................................................ 1113
13-10. 8-BPP Data Memory Organization .................................................................................. 1113
13-11. 4-BPP Data Memory Organization ................................................................................... 1113
13-12. 2-BPP Data Memory Organization ................................................................................... 1114
13-13. 1-BPP Data Memory Organization ................................................................................... 1114
13-14. Monochrome and Color Output....................................................................................... 1116
13-15. Example of Subpicture................................................................................................. 1117
13-16. Subpicture HOLS Bit................................................................................................... 1117
13-17. Raster Mode Display Format ......................................................................................... 1118
13-18. Palette Lookup Examples ............................................................................................. 1126
13-19. PID Register............................................................................................................. 1130
13-20. CTRL Register .......................................................................................................... 1131
13-21. LIDD_CTRL Register .................................................................................................. 1132
13-22. LIDD_CS0_CONF Register ........................................................................................... 1133
13-23. LIDD_CS0_ADDR Register ........................................................................................... 1134
13-24. LIDD_CS0_DATA Register............................................................................................ 1135
13-25. LIDD_CS1_CONF Register ........................................................................................... 1136
13-26. LIDD_CS1_ADDR Register ........................................................................................... 1137
13-27. LIDD_CS1_DATA Register............................................................................................ 1138
13-28. RASTER_CTRL Register.............................................................................................. 1139
30
List of Figures SPRUH73H–October 2011–Revised April 2013
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