bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 0
Row 1
Row 2
Row 3
Row 252
Row 253
Row 254
Row 255
P1o
P1o P1o P1o
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 0
Row 1
Row 2
Row 3
Row 252
Row 253
Row 254
Row 255
P1o
P2o P2o
P1o P1o P1o
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 0
Row 1
Row 2
Row 3
Row 252
Row 253
Row 254
Row 255
P1o
P1o P1o P1o
bit7 bit5 bit 3 bit1
bit7 bit5 bit 3 bit1
bit7 bit5 bit 3 bit1
bit7 bit5 bit 3 bit1
bit7 bit5 bit 3 bit1
bit7 bit5 bit 3 bit1
bit7 bit5 bit 3 bit1
bit7 bit5 bit 3 bit1
P1o
P1o P1o P1o
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 0
Row 1
Row 2
Row 3
Row 252
Row 253
Row 254
Row 255
P1o
P2o P2o
P1o P1o P1o
bit7 bit5 bit3 bit2 bit1 bit0
bit7 bit5 bit3 bit2 bit1 bit0
bit7 bit5 bit3 bit2 bit1
bit7 bit5 bit3 bit2 bit1
bit7 bit5 bit3 bit1
bit7 bit5 bit3 bit1
bit7 bit5 bit3 bit1
bit7 bit5 bit3 bit1
P1o
P2o P2o
P1o P1o P1o
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GPMC
Table 7-12. ECC Enable Settings
Bit Field Register Value Comments
ECCCS GPMC_ECC_CONFIG 0-3h Selects the chip-select where ECC is computed
ECC16B GPMC_ECC_CONFIG 0/1 Selects column number for ECC calculation
ECCCLEAR GPMC_ECC_CONTROL 0-7h Clears all ECC result registers
ECCPOINTER GPMC_ECC_CONTROL 0-7h A write to this bit field selects the ECC result register where
the first ECC computation is stored. Set to 1 by default.
ECCSIZE1 GPMC_ECC_SIZE_CONFIG 0-FFh Defines ECCSIZE1
ECCSIZE0 GPMC_ECC_SIZE_CONFIG 0-FFh Defines ECCSIZE0
ECCjRESULTSIZE GPMC_ECC_SIZE_CONFIG 0/1 Selects the size of ECCn result register
(j from 1 to 9)
ECCENABLE GPMC_ECC_CONFIG 1 Enables the ECC computation
7.1.3.3.12.3.1.3 ECC Computation
The ECC algorithm is a multiple parity bit accumulation computed on the odd and even bit streams
extracted from the byte or Word 16 streams. The parity accumulation is split into row and column
accumulations, as shown in Figure 7-31 and Figure 7-32. The intermediate row and column parities are
used to compute the upper level row and column parities. Only the final computation of each parity bit is
used for ECC comparison and correction.
P1o = bit7 XOR bit5 XOR bit3 XOR bit1 on each byte of the data stream
P1e = bit6 XOR bit4 XOR bit2 XOR bit0 on each byte of the data stream
P2o = bit7 XOR bit6 XOR bit3 XOR bit2 on each byte of the data stream
P2e = bit5 XOR bit4 XOR bit1 XOR bit0 on each byte of the data stream
P4o = bit7 XOR bit6 XOR bit5 XOR bit4 on each byte of the data stream
P4e = bit3 XOR bit2 XOR bit1 XOR bit0 on each byte of the data stream
Each column parity bit is XORed with the previous accumulated value.
Figure 7-31. Hamming Code Accumulation Algorithm (1 of 2)
311
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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