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The direction of the MMCHS data buffers are controlled by ADPDATDIROQ signals. ADPDATDIROQ[i] =
1 sets the corresponding DAT signal(s) in read position (input) and ADPDATDIROQ[i] = 0 sets the
corresponding DAT signal(s) in write position (output). Additionally, the ADPDATDIRLS signals are
provided (with opposite polarity) to control the direction of external level shifters. The value of these
control signals for the various data modes are summarized in Table 18-6.
Table 18-6. ADPDATDIROQ and ADPDATDIRLS Signal States
MMC/SD MMC/SD MMC/SD SDIO SDIO
1-bit mode 4-bit mode 8-bit mode 1-bit mode 4-bit mode
DAT[0] ADPDATDIRLS[0] = ADPDATDIRLS[0] = ADPDATDIRLS[0] = ADPDATDIRLS[0] = ADPDATDIRLS[0] =
0 / 1 0 / 1 0 / 1 0 / 1 0 / 1
ADPDATDIROQ[0] ADPDATDIROQ[0] ADPDATDIROQ[0] ADPDATDIROQ[0]
= 1 / 0 = 1 / 0 = 1 / 0 = 1 / 0
DAT[2] ADPDATDIRLS[2] = ADPDATDIRLS[2] = ADPDATDIRLS[2] = ADPDATDIRLS[2] = ADPDATDIRLS[2] =
0 0 / 1 0 / 1 0 / 1 0 / 1
ADPDATDIROQ[2] ADPDATDIROQ[2] ADPDATDIROQ[2] ADPDATDIROQ[2] ADPDATDIROQ[2]
= 1 = 1 / 0 = 1 / 0 = 1 / 0 = 1 / 0
DAT[1] ADPDATDIRLS[1] = ADPDATDIRLS[1] = ADPDATDIRLS[1] = ADPDATDIRLS[1] = ADPDATDIRLS[1] =
0 0 / 1 0 / 1 0 0 / 1
DAT[3]
ADPDATDIROQ[1] ADPDATDIROQ[1] ADPDATDIROQ[1] ADPDATDIROQ[1] ADPDATDIROQ[1]
= 1 = 1 / 0 = 1 / 0 = 1 = 1 / 0
DAT[4] ADPDATDIRLS[3] = ADPDATDIRLS[3] = ADPDATDIRLS[3] = ADPDATDIRLS[3] = ADPDATDIRLS[3] =
0 0 0 / 1 0 0
DAT[5]
ADPDATDIROQ[3] ADPDATDIROQ[3] ADPDATDIROQ[3] ADPDATDIROQ[3] ADPDATDIROQ[3]
DAT[6]
= 1 = 1 = 1 / 0 = 1 = 1
DAT[7]
ADPDATIRLSx = 0 for input and 1 for output — these signals are not pinned out on this device.
ADPDATIROQx = 1 for output and 1 for input.
Grayed cells indicate that the data line is not used in the selected transfer mode.
3349
SPRUH73H–October 2011–Revised April 2013 Multimedia Card (MMC)
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