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I2C Registers
Table 21-12. I2C_IRQSTATUS_RAW Register Field Descriptions (continued)
Bit Field Type Reset Description
10 XUDF R/W 0h Transmit underflow status.
Writing into this bit has no effect.
I2C transmit mode only.
This read-only bit indicates whether the transmitter has experienced
underflow.
In master transmit mode, underflow occurs when the shift register is
empty, the transmit FIFO is empty, and there are still some bytes to
transmit (DCOUNT 0).
In slave transmit mode, underflow occurs when the shift register is
empty, the transmit FIFO is empty, and there are still some bytes to
transmit (read request from external I2C master).
XUDF is set to 1 when the I2C has recognized an underflow.
The core holds the line till the underflow cause has disappeared.
XUDF is clear when writing I2C_DATA register or resetting the I2C
(I2C_CON:I2C_EN = 0).
Value after reset is low.
0x0 = Normal operation
0x1 = Transmit underflow
9 AAS R/W 0h Address recognized as slave IRQ status.
I2C mode only.
This read only bit is set to 1 by the device when it has recognized its
own slave address (or one of the alternative own addresses), or an
address of all zeros (8 bits).
When this bit is set to 1 by the core, an interrupt is signaled to the
local host if the interrupt was enabled.
This bit can be cleared in 2 ways: One way is if the interrupt was
enabled, it will be cleared by writing 1 into this register (writing 0 has
no effect).
The other way is if the interrupt was not enabled, the AAS bit is reset
to 0 by restart or stop.
Value after reset is low.
0x0 = No action
0x1 = Address recognized
8 BF R/W 0h I2C mode only.
This read only bit is set to 1 by the device when the I2C bus became
free (after a transfer is ended on the bus stop condition detected).
This interrupt informs the Local Host that it can initiate its own I2C
transfer on the bus.
When this bit is set to 1 by the core, an interrupt is signaled to the
local host if the interrupt was enabled.
The CPU can only clear this bit by writing a 1 into this register.
Writing 0 has no effect.
Value after reset is low.
0x0 = No action
0x1 = Bus Free
7 AERR R/W 0h Access Error IRQ status.
I2C mode only.
This read/clear only bit is set to 1 by the device if an Interface/OCP
write access is performed to I2C_DATA while the TX FIFO is full or if
an Interface/OCP read access is performed to the I2C_DATA while
the RX FIFO is empty.
Note that, when the RX FIFO is empty, a read access will return to
the previous read data value.
When the TX FIFO is full, a write access is ignored.
In both events, the FIFO pointers will not be updated.
When this bit is set to 1 by the core, an interrupt is signaled to the
local host if the interrupt was enabled.
The CPU can only clear this bit by writing a 1 into this register.
Writing 0 has no effect.
Value after reset is low.
0x0 = No action
0x1 = Access Error
3723
SPRUH73H–October 2011–Revised April 2013 I2C
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