I2C Registers
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Table 21-12. I2C_IRQSTATUS_RAW Register Field Descriptions (continued)
Bit Field Type Reset Description
6 STC R/W 0h Start Condition IRQ status.
I2C mode only.
This read/clear only bit is set to 1 by the device if previously the
module was in idle mode and a start condition was asynchronously
detected on the I2C Bus and signalized with an Wakeup (if the
I2C_SYSC.ClockActivity allows the system clock to be cut-off).
When the Active Mode will be restored and the interrupt generated,
this bit will indicate the reason of the wakeup.
Note
1: The corresponding interrupt for this bit should be enabled only if
the module was configured to allow the possibility of cutting-off the
system clock while in Idle State (I2C_SYSC.ClockActivity = 00 or
01).
Note
2: The first transfer (corresponding to the detected start condition)
will be lost (not taken into account by the module) and it will be used
only for generating the WakeUp enable for restoring the Active Mode
of the module.
On the I2C line, the external master which generated the transfer will
detect this behavior as a not acknowledge to the address phase and
will possibly restart the transfer.
The CPU can only clear this bit by writing a 1 into this register.
Writing 0 has no effect.
Value after reset is low.
0x0 = No action
0x1 = Start Condition detected
5 GC R/W 0h General call IRQ status.
Set to '1' by core when General call address detected and interrupt
signaled to MPUSS.
Write '1' to clear.
I2C mode only.
This read/clear only bit is set to 1 by the device if it detects the
address of all zeros (8 bits) (general call).
When this bit is set to 1 by the core, an interrupt is signaled to the
local host if the interrupt was enabled.
The CPU can only clear this bit by writing a 1 into this register.
Writing 0 has no effect.
Note: When this bit is set to 1, AAS also reads as 1.
Value after reset is low.
0x0 = No general call detected
0x1 = General call address detected
3724
I2C SPRUH73H–October 2011–Revised April 2013
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