Functional Description
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Table 26-15. 4th NAND ID Data Byte
I/O #
Item Description
7 6 5 4 3 2 1 0
1kB 0 0
2kB 0 1
Page Size
4kB 1 0
8kB 1 1
2 levels 0 0
4 levels 0 1
Cell type
8 levels 1 0
16 levels 1 1
64kB 0 0
128kB 0 1
Block Size
256kB 1 0
512kB 1 1
Reading NAND Geometry From I2C EEPROM
ROM supports a special boot mode called NANDI2C to support NAND devices whose geometry cannot be
detected by the ROM automatically using methods described in the previous section. If this boot mode is
selected, the ROM code tries to read NAND geometry from an I2C EEPROM. If the read is successful,
ROM code then proceeds to next steps of NAND boot, beginning with reading bad blocks information.
The list of device pins that are configured by the ROM in the case of NANDI2C boot mode. (This is in
addition to the NAND boot pins described in the previous sections.)
Table 26-16. Pins Used for NANDI2C Boot for I2C EEPROM Access
Signal name Pin Used in Device
I2C SCL i2c0_scl
I2C SDA i2c0_sda
ROM accesses the I2C EEPROM at I2C slave address 0x50 and reads 7 bytes starting from address
offset 0x80. The format of this (NAND geometry information) is as follows:
Table 26-17. NAND Geometry Information on I2C EEPROM
Byte address Information
Upper nibble Lower nibble
0x80 Magic Number – 0x10
0x81 Magic Number – 0xb3
0x82 Magic Number – 0x57
0x83 Magic Number – 0xa6
NAND column address (word/byte offset NAND row address (page offset) size in
0x84
within a page) size in bytes, Example: 2 bytes. Example: 3
Page size (2
N
) exponent “N”. Example (for Pages per block (2
N
) exponent
0x85
page size of 2048): 11 “N”Example (for number of blocks 64): 6
ECC Type
NAND bus width 00b = No ECC
0x86
0 = 8-bit device 01b = BCH8
1 = 16-bit device 10b = BCH16
11b = Reserved
4122
Initialization SPRUH73H–October 2011–Revised April 2013
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