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13.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h] ............................................... 1153
13.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h] ...................................................... 1155
13.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h] ................................................ 1157
13.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h] ............................................ 1159
13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h] .................................................. 1161
13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h] .................................................... 1162
14 Ethernet Subsystem ....................................................................................................... 1163
14.1 Introduction .............................................................................................................. 1164
14.1.1 Features ....................................................................................................... 1164
14.1.2 Unsupported Features ....................................................................................... 1165
14.2 Integration ............................................................................................................... 1166
14.2.1 Ethernet Switch Connectivity Attributes ................................................................... 1167
14.2.2 Ethernet Switch Clock and Reset Management .......................................................... 1168
14.2.3 Ethernet Switch Pin List ..................................................................................... 1169
14.2.4 Ethernet Switch RMII Clocking Details .................................................................... 1169
14.2.5 GMII Interface Signal Connections and Descriptions .................................................... 1170
14.2.6 RMII Signal Connections and Descriptions ............................................................... 1173
14.2.7 RGMII Signal Connections and Descriptions ............................................................. 1174
14.3 Functional Description ................................................................................................. 1176
14.3.1 CPSW_3G Subsystem ....................................................................................... 1176
14.3.2 CPSW_3G ..................................................................................................... 1181
14.3.3 Ethernet Mac Sliver (CPGMAC_SL) ....................................................................... 1223
14.3.4 Command IDLE ............................................................................................... 1225
14.3.5 RMII Interface ................................................................................................. 1225
14.3.6 RGMII Interface ............................................................................................... 1226
14.3.7 Common Platform Time Sync (CPTS) ..................................................................... 1228
14.3.8 MDIO ........................................................................................................... 1233
14.4 Software Operation ..................................................................................................... 1235
14.4.1 Transmit Operation ........................................................................................... 1235
14.4.2 Receive Operation ........................................................................................... 1237
14.4.3 Initializing the MDIO Module ................................................................................ 1238
14.4.4 Writing Data to a PHY Register ............................................................................ 1238
14.4.5 Reading Data from a PHY Register ........................................................................ 1239
14.4.6 Initialization and Configuration of CPSW .................................................................. 1239
14.5 Ethernet Subsystem Registers ....................................................................................... 1240
14.5.1 CPSW_ALE Registers ....................................................................................... 1240
14.5.2 CPSW_CPDMA Registers .................................................................................. 1255
14.5.3 CPSW_CPTS Registers ..................................................................................... 1308
14.5.4 CPSW_STATS Registers ................................................................................... 1321
14.5.5 CPDMA_STATERAM Registers ............................................................................ 1321
14.5.6 CPSW_PORT Registers ..................................................................................... 1355
14.5.7 CPSW_SL Registers ......................................................................................... 1410
14.5.8 CPSW_SS Registers ........................................................................................ 1424
14.5.9 CPSW_WR Registers ........................................................................................ 1437
14.5.10 Management Data Input/Output (MDIO) Registers ..................................................... 1473
15 Pulse-Width Modulation Subsystem (PWMSS) ................................................................... 1485
15.1 Pulse-Width Modulation Subsystem (PWMSS) .................................................................... 1486
15.1.1 Introduction .................................................................................................... 1486
15.1.2 Integration ..................................................................................................... 1488
15.1.3 PWMSS Registers ........................................................................................... 1489
15.2 Enhanced PWM (ePWM) Module .................................................................................... 1494
15.2.1 Introduction .................................................................................................... 1494
15.2.2 Functional Description ....................................................................................... 1498
8
Contents SPRUH73H–October 2011–Revised April 2013
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