Texas Instruments AM335 Series Technical Reference Manual

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12.3.6 DMA Requests ................................................................................................ 1027
12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1027
12.4 Operational Modes ..................................................................................................... 1029
12.4.1 PenCtrl and PenIRQ ......................................................................................... 1030
12.5 Touchscreen Controller Registers .................................................................................... 1033
12.5.1 TSC_ADC_SS Registers .................................................................................... 1033
13 LCD Controller ............................................................................................................... 1097
13.1 Introduction .............................................................................................................. 1098
13.1.1 Purpose of the Peripheral ................................................................................... 1098
13.1.2 Features ....................................................................................................... 1099
13.2 Integration ............................................................................................................... 1100
13.2.1 LCD Controller Connectivity Attributes .................................................................... 1100
13.2.2 LCD Controller Clock and Reset Management ........................................................... 1101
13.2.3 LCD Controller Pin List ...................................................................................... 1101
13.3 Functional Description ................................................................................................. 1102
13.3.1 Clocking ........................................................................................................ 1102
13.3.2 LCD External I/O Signals .................................................................................... 1104
13.3.3 DMA Engine ................................................................................................... 1105
13.3.4 LIDD Controller ............................................................................................... 1106
13.3.5 Raster Controller ............................................................................................. 1108
13.3.6 Interrupt Conditions .......................................................................................... 1119
13.3.7 DMA ............................................................................................................ 1121
13.3.8 Power Management .......................................................................................... 1121
13.4 Programming Model .................................................................................................... 1122
13.4.1 LCD Character Displays ..................................................................................... 1122
13.4.2 Active Matrix Displays ....................................................................................... 1125
13.4.3 System Interaction ........................................................................................... 1125
13.4.4 Palette Lookup ................................................................................................ 1125
13.4.5 Test Logic ..................................................................................................... 1127
13.4.6 Disable and Software Reset Sequence ................................................................... 1127
13.4.7 Precedence Order for Determining Frame Buffer Type ................................................. 1128
13.5 LCD Registers .......................................................................................................... 1128
13.5.1 PID Register (offset = 0h) [reset = 0h] ..................................................................... 1130
13.5.2 CTRL Register (offset = 4h) [reset = 0h] .................................................................. 1131
13.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h] .......................................................... 1132
13.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h] .................................................. 1133
13.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h] .................................................. 1134
13.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h] .................................................. 1135
13.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h] ................................................. 1136
13.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h] .................................................. 1137
13.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h] .................................................. 1138
13.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h] ................................................... 1139
13.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h] ............................................. 1141
13.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h] ............................................. 1142
13.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h] ............................................. 1143
13.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h] ........................................... 1145
13.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h] ......................................... 1146
13.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h] .................................................. 1147
13.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h] ............................................ 1148
13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h] ........................................ 1149
13.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h] ........................................... 1150
13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h] ........................................ 1151
13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h] ...................................................... 1152
7
SPRUH73H–October 2011–Revised April 2013 Contents
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English