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EDMA3 Registers
Table 11-25. EDMACC Registers (continued)
Offset Acronym Register Description Section
1088h QEECR QDMA Event Enable Clear Register Section 11.4.1.8.3
108Ch QEESR QDMA Event Enable Set Register Section 11.4.1.8.4
1090h QSER QDMA Secondary Event Register Section 11.4.1.8.5
1094h QSECR QDMA Secondary Event Clear Register Section 11.4.1.8.6
Shadow Region 0 Channel Registers
2000h ER Event Register
2004h ERH Event Register High
2008h ECR Event Clear Register
200Ch ECRH Event Clear Register High
2010h ESR Event Set Register
2014h ESRH Event Set Register High
2018h CER Chained Event Register
201Ch CERH Chained Event Register High
2020h EER Event Enable Register
2024h EERH Event Enable Register High
2028h EECR Event Enable Clear Register
202Ch EECRH Event Enable Clear Register High
2030h EESR Event Enable Set Register
2034h EESRH Event Enable Set Register High
2038h SER Secondary Event Register
203Ch SERH Secondary Event Register High
2040h SECR Secondary Event Clear Register
2044h SECRH Secondary Event Clear Register High
2050h IER Interrupt Enable Register
2054h IERH Interrupt Enable Register High
2058h IECR Interrupt Enable Clear Register
205Ch IECRH Interrupt Enable Clear Register High
2060h IESR Interrupt Enable Set Register
2064h IESRH Interrupt Enable Set Register High
2068h IPR Interrupt Pending Register
206Ch IPRH Interrupt Pending Register High
2070h ICR Interrupt Clear Register
2074h ICRH Interrupt Clear Register High
2078h IEVAL Interrupt Evaluate Register
2080h QER QDMA Event Register
2084h QEER QDMA Event Enable Register
2088h QEECR QDMA Event Enable Clear Register
208Ch QEESR QDMA Event Enable Set Register
2090h QSER QDMA Secondary Event Register
2094h QSECR QDMA Secondary Event Clear Register
2200h-2294h - Shadow Region 1 Channel Registers
2400h-2494h - Shadow Region 2 Channel Registers
... ...
2E00h-2E94h - Shadow Channel Registers for MP Space 7
941
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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