EDMA3 Registers
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The IECR is shown in Figure 11-90 and described in Table 11-74. The IECRH is shown in Figure 11-91
and described in Table 11-75.
Figure 11-90. Interrupt Enable Clear Register (IECR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 11-74. Interrupt Enable Clear Register (IECR) Field Descriptions
Bit Field Value Description
31-0 En Interrupt enable clear for channels 0-31.
0 No effect.
1 Corresponding bit in the interrupt enable register (IER) is cleared (In = 0).
Figure 11-91. Interrupt Enable Clear Register High (IECRH)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 11-75. Interrupt Enable Clear Register High (IECRH) Field Descriptions
Bit Field Value Description
31-0 En Interrupt enable clear for channels 32-63.
0 No effect.
1 Corresponding bit in the interrupt enable register high (IERH) is cleared (In = 0).
982
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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