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Enhanced PWM (ePWM) Module
Table 15-25. EPWMx Initialization for Figure 15-29
Register Bit Value Comments
TBPRD TBPRD 600 (258h) Period = 601 TBCLK counts
TBPHS TBPHS 0 Clear Phase Register to 0
TBCNT TBCNT 0 Clear TB counter
TBCTL CTRMODE TB_UP
PHSEN TB_DISABLE Phase loading disabled
PRDLD TB_SHADOW
SYNCOSEL TB_SYNC_DISABLE
HSPCLKDIV TB_DIV1 TBCLK = SYSCLK
CLKDIV TB_DIV1
CMPA CMPA 200 (C8h) Compare A = 200 TBCLK counts
CMPB CMPB 400 (190h) Compare B = 400 TBCLK counts
CMPCTL SHDWAMODE CC_SHADOW
SHDWBMODE CC_SHADOW
LOADAMODE CC_CTR_ZERO Load on CTR = 0
LOADBMODE CC_CTR_ZERO Load on CTR = 0
AQCTLA CAU AQ_SET
CBU AQ_CLEAR
AQCTLB ZRO AQ_TOGGLE
Table 15-26. EPWMx Run Time Changes for Figure 15-29
Register Bit Value Comments
CMPA CMPA EdgePosA Adjust duty for output EPWM1A
CMPB CMPB EdgePosB
1527
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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