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7-90. DDR2/3/mDDR Memory Controller FIFO Block Diagram........................................................... 407
7-91. EMIF_MOD_ID_REV Register ......................................................................................... 424
7-92. STATUS Register ........................................................................................................ 425
7-93. SDRAM_CONFIG Register............................................................................................. 426
7-94. SDRAM_CONFIG_2 Register.......................................................................................... 428
7-95. SDRAM_REF_CTRL Register ......................................................................................... 429
7-96. SDRAM_REF_CTRL_SHDW Register................................................................................ 430
7-97. SDRAM_TIM_1 Register................................................................................................ 431
7-98. SDRAM_TIM_1_SHDW Register ...................................................................................... 432
7-99. SDRAM_TIM_2 Register................................................................................................ 433
7-100. SDRAM_TIM_2_SHDW Register ...................................................................................... 434
7-101. SDRAM_TIM_3 Register................................................................................................ 435
7-102. SDRAM_TIM_3_SHDW Register ...................................................................................... 436
7-103. PWR_MGMT_CTRL Register .......................................................................................... 437
7-104. PWR_MGMT_CTRL_SHDW Register ................................................................................ 439
7-105. Interface Configuration Register ....................................................................................... 440
7-106. Interface Configuration Value 1 Register ............................................................................. 441
7-107. Interface Configuration Value 2 Register ............................................................................. 442
7-108. PERF_CNT_1 Register ................................................................................................. 443
7-109. PERF_CNT_2 Register ................................................................................................. 444
7-110. PERF_CNT_CFG Register ............................................................................................. 445
7-111. PERF_CNT_SEL Register.............................................................................................. 446
7-112. PERF_CNT_TIM Register .............................................................................................. 447
7-113. READ_IDLE_CTRL Register ........................................................................................... 448
7-114. READ_IDLE_CTRL_SHDW Register ................................................................................. 449
7-115. IRQSTATUS_RAW_SYS Register .................................................................................... 450
7-116. IRQSTATUS_SYS Register ............................................................................................ 451
7-117. IRQENABLE_SET_SYS Register...................................................................................... 452
7-118. IRQENABLE_CLR_SYS Register ..................................................................................... 453
7-119. ZQ_CONFIG Register................................................................................................... 454
7-120. Read-Write Leveling Ramp Window Register........................................................................ 455
7-121. Read-Write Leveling Ramp Control Register......................................................................... 456
7-122. Read-Write Leveling Control Register................................................................................. 457
7-123. DDR_PHY_CTRL_1 Register .......................................................................................... 458
7-124. DDR_PHY_CTRL_1_SHDW Register ................................................................................ 460
7-125. Priority to Class of Service Mapping Register........................................................................ 462
7-126. Connection ID to Class of Service 1 Mapping Register............................................................. 463
7-127. Connection ID to Class of Service 2 Mapping Register............................................................. 464
7-128. Read Write Execution Threshold Register............................................................................ 466
7-129. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0).................................................................. 469
7-130. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register(
CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) ........................................................................ 469
7-131. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) ...................................................................... 470
7-132. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0)).............................................................. 470
7-133. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) ..................................................................... 471
7-134. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
19
SPRUH73H–October 2011–Revised April 2013 List of Figures
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