www.ti.com
7-41. NAND Read Cycle Optimization Timing Description ................................................................ 333
7-42. Programming Model Top-Level Diagram ............................................................................. 336
7-43. NOR Interfacing Timing Parameters Diagram ....................................................................... 343
7-44. NAND Command Latch Cycle Timing Simplified Example......................................................... 347
7-45. Synchronous NOR Single Read Simplified Example................................................................ 352
7-46. Asynchronous NOR Single Write Simplified Example .............................................................. 354
7-47. GPMC Connection to an External NOR Flash Memory............................................................. 356
7-48. Synchronous Burst Read Access (Timing Parameters in Clock Cycles) ......................................... 358
7-49. Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ...................................... 360
7-50. Asynchronous Single Write Access (Timing Parameters in Clock Cycles)....................................... 362
7-51. GPMC_REVISION....................................................................................................... 367
7-52. GPMC_SYSCONFIG.................................................................................................... 367
7-53. GPMC_SYSSTATUS.................................................................................................... 368
7-54. GPMC_IRQSTATUS .................................................................................................... 369
7-55. GPMC_IRQENABLE .................................................................................................... 370
7-56. GPMC_TIMEOUT_CONTROL ......................................................................................... 371
7-57. GPMC_ERR_ADDRESS................................................................................................ 371
7-58. GPMC_ERR_TYPE...................................................................................................... 372
7-59. GPMC_CONFIG ......................................................................................................... 373
7-60. GPMC_STATUS ......................................................................................................... 374
7-61. GPMC_CONFIG1_i...................................................................................................... 375
7-62. GPMC_CONFIG2_i...................................................................................................... 377
7-63. GPMC_CONFIG3_i...................................................................................................... 378
7-64. GPMC_CONFIG4_i...................................................................................................... 380
7-65. GPMC_CONFIG5_i...................................................................................................... 382
7-66. GPMC_CONFIG6_i...................................................................................................... 383
7-67. GPMC_CONFIG7_i...................................................................................................... 384
7-68. GPMC_NAND_COMMAND_i .......................................................................................... 385
7-69. GPMC_NAND_ADDRESS_i............................................................................................ 385
7-70. GPMC_NAND_DATA_i ................................................................................................. 385
7-71. GPMC_PREFETCH_CONFIG1........................................................................................ 386
7-72. GPMC_PREFETCH_CONFIG2........................................................................................ 388
7-73. GPMC_PREFETCH_CONTROL....................................................................................... 388
7-74. GPMC_PREFETCH_STATUS ......................................................................................... 389
7-75. GPMC_ECC_CONFIG .................................................................................................. 390
7-76. GPMC_ECC_CONTROL ............................................................................................... 391
7-77. GPMC_ECC_SIZE_CONFIG........................................................................................... 392
7-78. GPMC_ECCj_RESULT ................................................................................................. 394
7-79. GPMC_BCH_RESULT0_i .............................................................................................. 395
7-80. GPMC_BCH_RESULT1_i .............................................................................................. 395
7-81. GPMC_BCH_RESULT2_i .............................................................................................. 395
7-82. GPMC_BCH_RESULT3_i .............................................................................................. 396
7-83. GPMC_BCH_SWDATA ................................................................................................. 396
7-84. GPMC_BCH_RESULT4_i .............................................................................................. 396
7-85. GPMC_BCH_RESULT5_i .............................................................................................. 397
7-86. GPMC_BCH_RESULT6_i .............................................................................................. 397
7-87. OCMC RAM Integration................................................................................................. 399
7-88. DDR2/3/mDDR Memory Controller Signals .......................................................................... 404
7-89. DDR2/3/mDDR Subsystem Block Diagram .......................................................................... 406
18
List of Figures SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
