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6-41. INTC_MIR_CLEAR3 Register.......................................................................................... 243
6-42. INTC_MIR_SET3 Register.............................................................................................. 244
6-43. INTC_ISR_SET3 Register .............................................................................................. 245
6-44. INTC_ISR_CLEAR3 Register .......................................................................................... 246
6-45. INTC_PENDING_IRQ3 Register....................................................................................... 247
6-46. INTC_PENDING_FIQ3 Register ....................................................................................... 248
6-47. INTC_ILR0 to INTC_ILR127 Register................................................................................. 249
7-1. GPMC Block Diagram................................................................................................... 253
7-2. GPMC Integration........................................................................................................ 254
7-3. GPMC to 16-Bit Address/Data-Multiplexed Memory ................................................................ 258
7-4. GPMC to 16-Bit Non-multiplexed Memory............................................................................ 259
7-5. GPMC to 8-Bit NAND Device .......................................................................................... 259
7-6. Chip-Select Address Mapping and Decoding Mask................................................................. 264
7-7. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ...................... 267
7-8. Wait Behavior During a Synchronous Read Burst Access ......................................................... 269
7-9. Read to Read for an Address-Data Multiplexed Device, On Different CS, Without Bus Turnaround (CS0n
Attached to Fast Device)................................................................................................ 271
7-10. Read to Read / Write for an Address-Data Multiplexed Device, On Different CS, With Bus Turnaround.... 271
7-11. Read to Read / Write for a Address-Data or AAD-Multiplexed Device, On Same CS, With Bus
Turnaround................................................................................................................ 272
7-12. Asynchronous Single Read Operation on an Address/Data Multiplexed Device................................ 281
7-13. Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device (32-Bit Read Split
Into 2 × 16-Bit Read) .................................................................................................... 282
7-14. Asynchronous Single Write on an Address/Data-Multiplexed Device............................................. 283
7-15. Asynchronous Single-Read on an AAD-Multiplexed Device ....................................................... 284
7-16. Asynchronous Single Write on an AAD-Multiplexed Device ....................................................... 286
7-17. Synchronous Single Read (GPMCFCLKDIVIDER = 0)............................................................. 288
7-18. Synchronous Single Read (GPMCFCLKDIVIDER = 1)............................................................. 289
7-19. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0) .................................................. 291
7-20. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1) .................................................. 292
7-21. Synchronous Single Write on an Address/Data-Multiplexed Device.............................................. 293
7-22. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode .................................. 294
7-23. Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode........................ 295
7-24. Asynchronous Single Read on an Address/Data-Nonmultiplexed Device ....................................... 297
7-25. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device........................................ 298
7-26. Asynchronous Multiple (Page Mode) Read........................................................................... 299
7-27. NAND Command Latch Cycle.......................................................................................... 304
7-28. NAND Address Latch Cycle ............................................................................................ 305
7-29. NAND Data Read Cycle ................................................................................................ 306
7-30. NAND Data Write Cycle................................................................................................. 307
7-31. Hamming Code Accumulation Algorithm (1 of 2).................................................................... 311
7-32. Hamming Code Accumulation Algorithm (2 of 2).................................................................... 312
7-33. ECC Computation for a 256-Byte Data Stream (Read or Write) .................................................. 312
7-34. ECC Computation for a 512-Byte Data Stream (Read or Write) .................................................. 313
7-35. 128 Word16 ECC Computation ........................................................................................ 314
7-36. 256 Word16 ECC Computation ........................................................................................ 314
7-37. Manual Mode Sequence and Mapping................................................................................ 319
7-38. NAND Page Mapping and ECC: Per-Sector Schemes ............................................................. 324
7-39. NAND Page Mapping and ECC: Pooled Spare Schemes.......................................................... 325
7-40. NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC..................................... 326
17
SPRUH73H–October 2011–Revised April 2013 List of Figures
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