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List of Figures
3-1. Microprocessor Unit (MPU) Subsystem............................................................................... 165
3-2. Microprocessor Unit (MPU) Subsystem Signal Interface ........................................................... 167
3-3. MPU Subsystem Clocking Scheme ................................................................................... 168
3-4. Reset Scheme of the MPU Subsystem ............................................................................... 169
3-5. MPU Subsystem Power Domain Overview........................................................................... 172
5-1. SGX530 Integration...................................................................................................... 182
5-2. SGX Block Diagram ..................................................................................................... 184
6-1. Interrupt Controller Block Diagram .................................................................................... 187
6-2. IRQ/FIQ Processing Sequence ........................................................................................ 193
6-3. Nested IRQ/FIQ Processing Sequence .............................................................................. 197
6-4. INTC_REVISION Register.............................................................................................. 206
6-5. INTC_SYSCONFIG Register........................................................................................... 207
6-6. INTC_SYSSTATUS Register........................................................................................... 208
6-7. INTC_SIR_IRQ Register ................................................................................................ 209
6-8. INTC_SIR_FIQ Register ................................................................................................ 210
6-9. INTC_CONTROL Register.............................................................................................. 211
6-10. INTC_PROTECTION Register ......................................................................................... 212
6-11. INTC_IDLE Register..................................................................................................... 213
6-12. INTC_IRQ_PRIORITY Register........................................................................................ 214
6-13. INTC_FIQ_PRIORITY Register ........................................................................................ 215
6-14. INTC_THRESHOLD Register .......................................................................................... 216
6-15. INTC_ITR0 Register ..................................................................................................... 217
6-16. INTC_MIR0 Register .................................................................................................... 218
6-17. INTC_MIR_CLEAR0 Register.......................................................................................... 219
6-18. INTC_MIR_SET0 Register.............................................................................................. 220
6-19. INTC_ISR_SET0 Register .............................................................................................. 221
6-20. INTC_ISR_CLEAR0 Register .......................................................................................... 222
6-21. INTC_PENDING_IRQ0 Register....................................................................................... 223
6-22. INTC_PENDING_FIQ0 Register ....................................................................................... 224
6-23. INTC_ITR1 Register ..................................................................................................... 225
6-24. INTC_MIR1 Register .................................................................................................... 226
6-25. INTC_MIR_CLEAR1 Register.......................................................................................... 227
6-26. INTC_MIR_SET1 Register.............................................................................................. 228
6-27. INTC_ISR_SET1 Register .............................................................................................. 229
6-28. INTC_ISR_CLEAR1 Register .......................................................................................... 230
6-29. INTC_PENDING_IRQ1 Register....................................................................................... 231
6-30. INTC_PENDING_FIQ1 Register ....................................................................................... 232
6-31. INTC_ITR2 Register ..................................................................................................... 233
6-32. INTC_MIR2 Register .................................................................................................... 234
6-33. INTC_MIR_CLEAR2 Register.......................................................................................... 235
6-34. INTC_MIR_SET2 Register.............................................................................................. 236
6-35. INTC_ISR_SET2 Register .............................................................................................. 237
6-36. INTC_ISR_CLEAR2 Register .......................................................................................... 238
6-37. INTC_PENDING_IRQ2 Register....................................................................................... 239
6-38. INTC_PENDING_FIQ2 Register ....................................................................................... 240
6-39. INTC_ITR3 Register ..................................................................................................... 241
6-40. INTC_MIR3 Register .................................................................................................... 242
16
List of Figures SPRUH73H–October 2011–Revised April 2013
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