GPMC_FCLK
GPMC_CLK
WAIT
Valid address
Write data
CSONTIME
CSWROFFTIME
ADVONTIME
ADVWROFFTIME
WEONTIME
WEOFFTIME
WRCYCLETIME
nBE1/nBE0
nCS
nADV
nWE
A[27:1]
D[15:0]
GPMC
www.ti.com
7.1.3.3.10.3.2 Asynchronous Single Write Operation on a Nonmultiplexed Device
Figure 7-25 shows an asynchronous single write operation on a nonmultiplexed device.
Figure 7-25. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device
The 27-bit address is driven onto the address bus A[27:1] and the 16-bit data is driven onto the data bus
D[15:0].
CSn, ADVn, WEn and DIR signals are controlled in the same way as address/data multiplexed accesses,
see Section 7.1.3.3.10.1.1.3.
298
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
