GPMC_FCLK
GPMC_CLK
WAIT
LSB AddMSB Address
Data 0
Data 0
Valid Address
CSONTIME
CSRDOFFTIME
ADVONTIME
ADVAADMUXONTIME
ADVRDOFFTIME
ADVAADMUXRDOFFTIME
OEAADMUXONTIME
OEONTIME
OEAADMUXOFFTIME
OEOFFTIME
RDCYCLETIME
RDACCESSTIME
nBE1/nBE0
nCS
nADV
nOE
A[16:1]/D[15:0]
A[27:17]
DIR
INOUT OUT
GPMC
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After a write operation, if no other access (read or write) is pending, the data bus keeps its previous value.
See Section 7.1.3.3.9.10.
7.1.3.3.10.1.1.5 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
Write multiple (page) access in asynchronous mode is not supported for address/data-multiplexed
devices. If GPMC_CONFIG1_i[28] WRITEMULTIPLE is enabled (1) with GPMC_CONFIG1_i[27]
WRITETYPE as asynchronous (0), the GPMC processes single asynchronous accesses.
For accesses on non-multiplexed devices, see Section 7.1.3.3.10.3.
7.1.3.3.10.1.2 Access on Address/Address/Data (AAD) Multiplexed Devices
7.1.3.3.10.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
Figure 7-15 shows an asynchronous single read operation on an AAD-multiplexed device.
Figure 7-15. Asynchronous Single-Read on an AAD-Multiplexed Device
284
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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