D[15:0]
Address
WEONTIME = 0
WEOFFTIME
ADVWROFFTIME = WRCYCLETIME
CSWROFFTIME = WRCYCLETIME
WRCYCLETIME
ADVONTIME = 0
CSONTIME = 0
nBE0/CLE
nCS
nWE
nADV/ALE
www.ti.com
GPMC
7.1.3.3.12.1.4 Address Latch Cycle
Writing data at the GPMC_NAND_ADDRESS_i location places the data as the NAND partial address
value on the bus, using a regular asynchronous write access.
• CSn is controlled by the CSONTIME and CSWROFFTIME timing parameters.
• ALE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters.
• WEn is controlled by the WEONTIME and WEOFFTIME timing parameters.
• CLE and REn (OEn) are maintained inactive.
Figure 7-28 shows the NAND address latch cycle.
ALE is shared with the ADVn output signal and has an inverted polarity from ADVn. The NAND qualifier
deals with this. During the asynchronous NAND data access cycle, ALE is kept stable.
Figure 7-28. NAND Address Latch Cycle
305
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
