Texas Instruments AM335 Series

GPMC_FCLK
GPMC_CLK
nBE1/nBE0
nCS
nADV
nWE
DIR
WAIT
Valid Address
Valid Address
D 0
D 3
D 4
D 5 D 6
D 7
D 7
OUT
CSONTIME
CSWROFFTIME
ADVONTIME
ADVWROFFTIME
WRDATAONADMUXBUS
WEONTIME
WEOFFTIME
CLKACTIVATIONTIME
WRACCESSTIME
WRCYCLETIME0
A[27:17]
A[16:1]/D[15:0]
D 1 D 2
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
WRCYCLETIME1
GPMC www.ti.com
7.1.3.3.10.2.4 Synchronous Multiple (Burst) Write
Synchronous burst write mode provides synchronous single or consecutive accesses. Figure 7-22 shows
a synchronous burst write access when the chip-select is configured in address/data-multiplexed mode.
Figure 7-22. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode
Figure 7-23 shows the same synchronous burst write access when the chip-select is configured in
address/address/data-multiplexed (AAD-multiplexed) mode.
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Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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