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(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) .................................................................... 472
7-135. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0).................................................................... 472
7-136. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) ................................................................. 473
7-137. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio
Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0).................................................... 473
7-138. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)............................................................. 474
7-139. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)...... 475
7-140. ELM Integration .......................................................................................................... 477
7-141. ELM Revision Register (ELM_REVISION) ........................................................................... 488
7-142. ELM System Configuration Register (ELM_SYSCONFIG)......................................................... 488
7-143. ELM System Status Register (ELM_SYSSTATUS) ................................................................. 489
7-144. ELM Interrupt Status Register (ELM_IRQSTATUS)................................................................. 490
7-145. ELM Interrupt Enable Register (ELM_IRQENABLE)................................................................ 492
7-146. ELM Location Configuration Register (ELM_LOCATION_CONFIG).............................................. 493
7-147. ELM Page Definition Register (ELM_PAGE_CTRL) ................................................................ 494
7-148. ELM_SYNDROME_FRAGMENT_0_i Register ...................................................................... 495
7-149. ELM_SYNDROME_FRAGMENT_1_i Register ...................................................................... 495
7-150. ELM_SYNDROME_FRAGMENT_2_i Register ...................................................................... 495
7-151. ELM_SYNDROME_FRAGMENT_3_i Register ...................................................................... 496
7-152. ELM_SYNDROME_FRAGMENT_4_i Register ...................................................................... 496
7-153. ELM_SYNDROME_FRAGMENT_5_i Register ...................................................................... 496
7-154. ELM_SYNDROME_FRAGMENT_6_i Register ...................................................................... 497
7-155. ELM_LOCATION_STATUS_i Register................................................................................ 497
7-156. ELM_ERROR_LOCATION_0-15_i Registers ........................................................................ 498
8-1. Functional and Interface Clocks ....................................................................................... 500
8-2. Generic Clock Domain .................................................................................................. 505
8-3. Clock Domain State Transitions ....................................................................................... 505
8-4. Generic Power Domain Architecture .................................................................................. 507
8-5. High Level System View for RTC-only Mode ........................................................................ 512
8-6. System Level View of Power Management of Cortex A8 MPU and Cortex M3 ................................. 515
8-7. IPC Mechanism .......................................................................................................... 516
8-8. ADPLLS ................................................................................................................... 520
8-9. Basic Structure of the ADPLLLJ ....................................................................................... 522
8-10. Core PLL .................................................................................................................. 525
8-11. Peripheral PLL Structure................................................................................................ 528
8-12. MPU Subsystem PLL Structure ........................................................................................ 530
8-13. Display PLL Structure ................................................................................................... 531
8-14. DDR PLL Structure ...................................................................................................... 532
8-15. CLKOUT Signals......................................................................................................... 533
8-16. Watchdog Timer Clock Selection ...................................................................................... 533
8-17. Timer Clock Selection ................................................................................................... 534
8-18. RTC, VTP, and Debounce Clock Selection .......................................................................... 535
8-19. PORz ...................................................................................................................... 537
8-20. External System Reset.................................................................................................. 538
8-21. Warm Reset Sequence (External Warm Reset Source)............................................................ 539
8-22. Warm Reset Sequence (Internal Warm Reset Source)............................................................. 540
8-23. CM_PER_L4LS_CLKSTCTRL Register .............................................................................. 550
20
List of Figures SPRUH73H–October 2011–Revised April 2013
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