H/W Mailbox
A8 has write permission,
CM3 has read-only permission
CM3 has write permission,
A8 has read-only permission
Not enforced by h/w
A8
CM3
R/WR/W
R/W
SEV instruction
31
16 15 0
IPC_MSG_REG0
IPC_MSG_REG1
IPC_MSG_REG3
IPC_MSG_REG2
IPC_MSG_REG4
IPC_MSG_REG5
IPC_MSG_REG6
IPC_MSG_REG7
Reserved for future use
Customer Use
CMD_IDCMD_STAT
Reserved for future use
Reserved for future use
Notification only
Reserved
CMD param2
CMD param1
Power, Reset, and Clock Management
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Figure 8-7. IPC Mechanism
IPC_MSG_REG1 contains the CMD_STAT and CMD_ID parameters as described in Table 8-15 and
Table 8-16.
Table 8-15. CMD_STAT Field
CMD_STAT Value Description
In the initialization phase, PASS (0x1) denotes that the CM3 was successfully
PASS 0x1
initialized.
IN_PROGRESS 0x2 Early indication of command being carried out.
In the initialization phase, 0x2 denotes CM3 could not properly initialize. When
other tasks are to be done, FAIL (0x3) indicates some error in carrying out the
FAIL 0x3
task.
Check trace vector for details.
CM3 INTC will catch the next WFI of A8 and continue with the pre-defined
WAIT4OK 0x4
sequence.
Table 8-16. CMD_ID Field
CMD_ID Value Description
1. Initiates force_sleep on interconnect clocks.
CMD_RTC 0x1
2. Turns off MPU and PER power domains.
3. Programs the RTC alarm register for deasserting pmic_pwr_enable.
CMD_RTC_FAST 0x2 Programs the RTC alarm register for deasserting pmic_pwr_enable.
1. Initiates force_sleep on interconnect clocks.
CMD_DS0 0x3
2. Turns off the MPU and PER power domains.
3. Configures the system for disabling MOSC when CM3 executes WFI.
1. Initiates force_sleep on interconnect clocks.
CMD_DS1 0x5
2. Turns off the MPU power domains.
3. Configures the system for disabling MOSC when CM3 executes WFI.
516
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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