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GPMC
Command and address values are not latched during the access and cannot be read back at the register
location.
• Only write accesses must be issued to these locations, but the GPMC does not discard any read
access. Accessing a NAND device with OEn and CLE or ALE asserted (read access) can produce
undefined results.
• Write accesses to the GPMC_NAND_COMMAND_i register location and to the
GPMC_NAND_ADDRESS_i register location must be posted for faster operations. The
GPMC_CONFIG[0] NANDFORCEPOSTEDWRITE bit enables write accesses to these locations as
posted, even if they are defined as nonposted.
A write buffer is used to store write transaction information before the external device is accessed:
• Up to eight consecutive posted write accesses can be accepted and stored in the write buffer.
• For nonposted write, the pipeline is one deep.
• A GPMC_STATUS[0] EMPTYWRITEBUFFERSTATUS bit stores the empty status of the write buffer.
The GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i registers are 32-bit word locations,
which means any 32-bit word or 16-bit word access is split into 4- or 2-byte accesses if an 8-bit wide
NAND device is attached. For multiple-command phase or multiple-address phase, the software driver can
use 32-bit word or 16-bit word access to these registers, but it must account for the splitting and little-
endian ordering scheme. When only one byte command or address phase is required, only byte write
access to a GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i can be used, and any of the
four byte locations of the registers are valid.
The same applies to GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i 32-bit word write
access to a 16-bit wide NAND device (split into two 16-bit word accesses). In the case of a 16-bit word
write access, the MSByte of the 16-bit word value must be set according to the NAND device requirement
(usually 0). Either 16-bit word location or any one of the four byte locations of the registers is valid
303
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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