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Table 7-19. Misaligned Nibble Mapping of Message in 16-bit NAND (1 Unused Nibble)
16-Bit Word
Byte Offset
4-Bit Most Significant Nibble 4-Bit Less Significant Nibble
0 Nibble S-3 Nibble S-4 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-7 Nibble S-8 Nibble S-5 Nibble S-6
⋮ ⋮ ⋮ ⋮ ⋮
(S+1)/2 - 4 Nibble 4 Nibble 3 Nibble 6 Nibble 5
(S+1)/2 - 2 Nibble 0 (LSB) Nibble 2 Nibble 1
Table 7-20. Misaligned Nibble Mapping of Message in 16-bit NAND (2 Unused Nibble)
16-Bit Word
Byte Offset
4-Bit Most Significant Nibble 4-Bit Less Significant Nibble
0 Nibble S-3 Nibble S-4 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-7 Nibble S-8 Nibble S-5 Nibble S-6
⋮ ⋮ ⋮ ⋮ ⋮
(S+2)/2 - 4 Nibble 3 Nibble 2 Nibble 5 Nibble 4
(S+2)/2 - 2 Nibble 1 Nibble 0 (LSB)
Table 7-21. Misaligned Nibble Mapping of Message in 16-bit NAND (3 Unused Nibble)
16-Bit Word
Byte Offset
4-Bit Most Significant Nibble 4-Bit Less Significant Nibble
0 Nibble S-3 Nibble S-4 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-7 Nibble S-8 Nibble S-5 Nibble S-6
⋮ ⋮ ⋮ ⋮ ⋮
(S+3)/2 - 4 Nibble 2 Nibble 1 Nibble 4 Nibble 3
(S+3)/2 - 2 Nibble 0 (LSB)
Note that many other cases exist than the ones represented above, for example, where the message does
not start on a word boundary.
7.1.3.3.12.3.2.4 Memory Mapping of the ECC
The ECC (or remainder) is presented by the BCH module as a single 104-bit (or 52-bit), little-endian
vector. It is up to the software to fetch those 13 bytes (or 6 bytes) from the modules interface, then store
them to the NANDs spare area (page write) or to an intermediate buffer for comparison with the stored
ECC (page read). There are no constraints on the ECC mapping inside the spare area: it is a
softwarecontrolled operation.
However, it is advised to maintain a coherence in the respective formats of the message or the ECC
remainder once they have been read out of the NAND. The error correction algorithm works from the
complete codeword (concatenated message and remainder) once an error as been detected. The creation
of this codeword should be made as straightforward as possible.
318
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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