Texas Instruments AM335 Series Technical Reference Manual

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9.3.42 vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h] ................................................. 806
9.3.43 vdd_mpu_opp_100 Register (offset = 774h) [reset = 0h] ................................................. 807
9.3.44 vdd_mpu_opp_120 Register (offset = 778h) [reset = 0h] ................................................. 808
9.3.45 vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h] .............................................. 809
9.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h] ................................................ 810
9.3.47 vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h] ................................................ 811
9.3.48 bb_scale Register (offset = 7D0h) [reset = 0h] ............................................................ 812
9.3.49 usb_vid_pid Register (offset = 7F4h) [reset = 4516141h] ................................................ 813
9.3.50 efuse_sma Register (offset = 7FCh) [reset = 0h] .......................................................... 814
9.3.51 conf_<module>_<pin> Register (offset = 800h–A34h) ................................................... 815
9.3.52 cqdetect_status Register (offset = E00h) [reset = 0h] .................................................... 816
9.3.53 ddr_io_ctrl Register (offset = E04h) [reset = 0h] ........................................................... 817
9.3.54 vtp_ctrl Register (offset = E0Ch) [reset = 0h] .............................................................. 818
9.3.55 vref_ctrl Register (offset = E14h) [reset = 0h] .............................................................. 819
9.3.56 tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h] ................................................. 820
9.3.57 tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h] ................................................. 821
9.3.58 tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h] ............................................... 822
9.3.59 tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h] ............................................. 823
9.3.60 tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h] .............................................. 824
9.3.61 tpcc_evt_mux_20_23 Register (offset = FA4h) [reset = 0h] .............................................. 825
9.3.62 tpcc_evt_mux_24_27 Register (offset = FA8h) [reset = 0h] .............................................. 826
9.3.63 tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h] ............................................. 827
9.3.64 tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h] .............................................. 828
9.3.65 tpcc_evt_mux_36_39 Register (offset = FB4h) [reset = 0h] .............................................. 829
9.3.66 tpcc_evt_mux_40_43 Register (offset = FB8h) [reset = 0h] .............................................. 830
9.3.67 tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h] ............................................. 831
9.3.68 tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h] ............................................. 832
9.3.69 tpcc_evt_mux_52_55 Register (offset = FC4h) [reset = 0h] ............................................. 833
9.3.70 tpcc_evt_mux_56_59 Register (offset = FC8h) [reset = 0h] ............................................. 834
9.3.71 tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h] ............................................. 835
9.3.72 timer_evt_capt Register (offset = FD0h) [reset = 0h] ..................................................... 836
9.3.73 ecap_evt_capt Register (offset = FD4h) [reset = 0h] ..................................................... 837
9.3.74 adc_evt_capt Register (offset = FD8h) [reset = 0h] ....................................................... 838
9.3.75 reset_iso Register (offset = 1000h) [reset = 0h] ........................................................... 839
9.3.76 dpll_pwr_sw_ctrl Register (offset = 1318h) [reset = 0h] .................................................. 840
9.3.77 ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h] ....................................................... 842
9.3.78 sma2 Register (offset = 1320h) [reset = 0h] ................................................................ 843
9.3.79 m3_txev_eoi Register (offset = 1324h) [reset = 0h] ....................................................... 844
9.3.80 ipc_msg_reg0 Register (offset = 1328h) [reset = 0h] ..................................................... 845
9.3.81 ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h] ..................................................... 846
9.3.82 ipc_msg_reg2 Register (offset = 1330h) [reset = 0h] ..................................................... 847
9.3.83 ipc_msg_reg3 Register (offset = 1334h) [reset = 0h] ..................................................... 848
9.3.84 ipc_msg_reg4 Register (offset = 1338h) [reset = 0h] ..................................................... 849
9.3.85 ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h] ..................................................... 850
9.3.86 ipc_msg_reg6 Register (offset = 1340h) [reset = 0h] ..................................................... 851
9.3.87 ipc_msg_reg7 Register (offset = 1344h) [reset = 0h] ..................................................... 852
9.3.88 ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h] ................................................... 853
9.3.89 ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h] ................................................... 855
9.3.90 ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h] .................................................. 857
9.3.91 ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h] ................................................... 859
9.3.92 ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h] ................................................... 861
10 Interconnects .................................................................................................................. 863
10.1 Introduction ............................................................................................................... 864
5
SPRUH73H–October 2011–Revised April 2013 Contents
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English