Texas Instruments AM335 Series Technical Reference Manual

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9-75. timer_evt_capt Register................................................................................................. 836
9-76. ecap_evt_capt Register ................................................................................................. 837
9-77. adc_evt_capt Register................................................................................................... 838
9-78. reset_iso Register........................................................................................................ 839
9-79. dpll_pwr_sw_ctrl Register............................................................................................... 840
9-80. ddr_cke_ctrl Register.................................................................................................... 842
9-81. sma2 Register ............................................................................................................ 843
9-82. m3_txev_eoi Register ................................................................................................... 844
9-83. ipc_msg_reg0 Register.................................................................................................. 845
9-84. ipc_msg_reg1 Register.................................................................................................. 846
9-85. ipc_msg_reg2 Register.................................................................................................. 847
9-86. ipc_msg_reg3 Register.................................................................................................. 848
9-87. ipc_msg_reg4 Register.................................................................................................. 849
9-88. ipc_msg_reg5 Register.................................................................................................. 850
9-89. ipc_msg_reg6 Register.................................................................................................. 851
9-90. ipc_msg_reg7 Register.................................................................................................. 852
9-91. ddr_cmd0_ioctrl Register ............................................................................................... 853
9-92. ddr_cmd1_ioctrl Register ............................................................................................... 855
9-93. ddr_cmd2_ioctrl Register ............................................................................................... 857
9-94. ddr_data0_ioctrl Register ............................................................................................... 859
9-95. ddr_data1_ioctrl Register ............................................................................................... 861
10-1. L3 Topology............................................................................................................... 865
10-2. L4 Topology............................................................................................................... 868
11-1. EDMA3 Controller Block Diagram ..................................................................................... 870
11-2. TPCC Integration......................................................................................................... 873
11-3. TPTC Integration......................................................................................................... 874
11-4. EDMA3 Channel Controller (EDMA3CC) Block Diagram........................................................... 877
11-5. EDMA3 Transfer Controller (EDMA3TC) Block Diagram........................................................... 878
11-6. Definition of ACNT, BCNT, and CCNT ............................................................................... 879
11-7. A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................... 880
11-8. AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................. 881
11-9. PaRAM Set ............................................................................................................... 883
11-10. Channel Options Parameter (OPT).................................................................................... 885
11-11. Linked Transfer........................................................................................................... 892
11-12. Link-to-Self Transfer ..................................................................................................... 893
11-13. DMA Channel and QDMA Channel to PaRAM Mapping ........................................................... 898
11-14. QDMA Channel to PaRAM Mapping .................................................................................. 899
11-15. Shadow Region Registers .............................................................................................. 900
11-16. Interrupt Diagram ........................................................................................................ 904
11-17. Error Interrupt Operation................................................................................................ 907
11-18. PaRAM Set Content for Proxy Memory Protection Example....................................................... 911
11-19. Channel Options Parameter (OPT) Example ........................................................................ 911
11-20. Proxy Memory Protection Example.................................................................................... 912
11-21. EDMA3 Prioritization..................................................................................................... 919
11-22. Block Move Example .................................................................................................... 920
11-23. Block Move Example PaRAM Configuration ......................................................................... 920
11-24. Subframe Extraction Example.......................................................................................... 921
11-25. Subframe Extraction Example PaRAM Configuration............................................................... 921
11-26. Data Sorting Example ................................................................................................... 922
26
List of Figures SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English