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11-27. Data Sorting Example PaRAM Configuration ........................................................................ 923
11-28. Servicing Incoming McASP Data Example ........................................................................... 924
11-29. Servicing Incoming McASP Data Example PaRAM Configuration ................................................ 924
11-30. Servicing Peripheral Burst Example................................................................................... 925
11-31. Servicing Peripheral Burst Example PaRAM Configuration........................................................ 926
11-32. Servicing Continuous McASP Data Example ........................................................................ 927
11-33. Servicing Continuous McASP Data Example PaRAM Configuration ............................................. 928
11-34. Servicing Continuous McASP Data Example Reload PaRAM Configuration .................................... 929
11-35. Ping-Pong Buffering for McASP Data Example ..................................................................... 931
11-36. Ping-Pong Buffering for McASP Example PaRAM Configuration ................................................. 931
11-37. Ping-Pong Buffering for McASP Example Pong PaRAM Configuration .......................................... 932
11-38. Ping-Pong Buffering for McASP Example Ping PaRAM Configuration ........................................... 933
11-39. Intermediate Transfer Completion Chaining Example .............................................................. 934
11-40. Single Large Block Transfer Example................................................................................. 935
11-41. Smaller Packet Data Transfers Example ............................................................................. 935
11-42. Peripheral ID Register (PID)............................................................................................ 942
11-43. EDMA3CC Configuration Register (CCCFG) ........................................................................ 943
11-44. EDMA3CC System Configuration Register (SYSCONFIG) ........................................................ 945
11-45. DMA Channel Map n Registers (DCHMAPn) ........................................................................ 946
11-46. QDMA Channel Map n Registers (QCHMAPn) ...................................................................... 947
11-47. DMA Channel Queue n Number Registers (DMAQNUMn) ........................................................ 948
11-48. QDMA Channel Queue Number Register (QDMAQNUM) ......................................................... 949
11-49. Queue Priority Register (QUEPRI) .................................................................................... 950
11-50. Event Missed Register (EMR).......................................................................................... 951
11-51. Event Missed Register High (EMRH) ................................................................................. 951
11-52. Event Missed Clear Register (EMCR)................................................................................. 952
11-53. Event Missed Clear Register High (EMCRH) ........................................................................ 952
11-54. QDMA Event Missed Register (QEMR)............................................................................... 953
11-55. QDMA Event Missed Clear Register (QEMCR)...................................................................... 954
11-56. EDMA3CC Error Register (CCERR) .................................................................................. 954
11-57. EDMA3CC Error Clear Register (CCERRCLR)...................................................................... 955
11-58. Error Evaluation Register (EEVAL).................................................................................... 957
11-59. DMA Region Access Enable Register for Region m (DRAEm).................................................... 958
11-60. DMA Region Access Enable High Register for Region m (DRAEHm)............................................ 958
11-61. QDMA Region Access Enable for Region m (QRAEm)32-bit, 2 Rows ........................................... 959
11-62. Event Queue Entry Registers (QxEy) ................................................................................. 960
11-63. Queue Status Register n (QSTATn)................................................................................... 961
11-64. Queue Watermark Threshold A Register (QWMTHRA) ............................................................ 962
11-65. EDMA3CC Status Register (CCSTAT)................................................................................ 963
11-66. Memory Protection Fault Address Register (MPFAR) .............................................................. 965
11-67. Memory Protection Fault Status Register (MPFSR)................................................................. 966
11-68. Memory Protection Fault Command Register (MPFCR)............................................................ 967
11-69. Memory Protection Page Attribute Register (MPPAn) .............................................................. 968
11-70. Event Register (ER) ..................................................................................................... 970
11-71. Event Register High (ERH) ............................................................................................. 970
11-72. Event Clear Register (ECR) ............................................................................................ 971
11-73. Event Clear Register High (ECRH).................................................................................... 971
11-74. Event Set Register (ESR)............................................................................................... 972
11-75. Event Set Register High (ESRH) ...................................................................................... 973
27
SPRUH73H–October 2011–Revised April 2013 List of Figures
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