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15-30. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ............................................................................................... 1528
15-31. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ......................................................................................... 1530
15-32. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ....................................................................................................................... 1532
15-33. Dead-Band Generator Submodule................................................................................... 1534
15-34. Configuration Options for the Dead-Band Generator Submodule ............................................... 1535
15-35. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)................................................. 1537
15-36. PWM-Chopper Submodule............................................................................................ 1538
15-37. PWM-Chopper Submodule Signals and Registers ................................................................ 1539
15-38. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only .............................. 1540
15-39. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ..... 1540
15-40. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses.................................................................................................................... 1541
15-41. Trip-Zone Submodule.................................................................................................. 1542
15-42. Trip-Zone Submodule Mode Control Logic ......................................................................... 1545
15-43. Trip-Zone Submodule Interrupt Logic................................................................................ 1545
15-44. Event-Trigger Submodule ............................................................................................. 1546
15-45. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller ............................................. 1547
15-46. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs...................................... 1547
15-47. Event-Trigger Interrupt Generator.................................................................................... 1549
15-48. HRPWM System Interface ............................................................................................ 1550
15-49. Resolution Calculations for Conventionally Generated PWM .................................................... 1551
15-50. Operating Logic Using MEP .......................................................................................... 1552
15-51. Required PWM Waveform for a Requested Duty = 40.5% ....................................................... 1554
15-52. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz.............................. 1556
15-53. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz.............................. 1556
15-54. Simplified ePWM Module.............................................................................................. 1557
15-55. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .................................... 1558
15-56. Control of Four Buck Stages. Here F
PWM1
≠ F
PWM2
≠ F
PWM3
≠ F
PWM4
................................................. 1559
15-57. Buck Waveforms for (Note: Only three bucks shown here)....................................................... 1560
15-58. Control of Four Buck Stages. (Note: F
PWM2
= N × F
PWM1
)........................................................... 1562
15-59. Buck Waveforms for (Note: F
PWM2
= F
PWM1)
).......................................................................... 1563
15-60. Control of Two Half-H Bridge Stages (F
PWM2
= N × F
PWM1
)......................................................... 1565
15-61. Half-H Bridge Waveforms for (Note: Here F
PWM2
= F
PWM1
)......................................................... 1566
15-62. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................ 1568
15-63. 3-Phase Inverter Waveforms for (Only One Inverter Shown) .................................................... 1569
15-64. Configuring Two PWM Modules for Phase Control................................................................ 1572
15-65. Timing Waveforms Associated With Phase Control Between 2 Modules....................................... 1573
15-66. Control of a 3-Phase Interleaved DC/DC Converter............................................................... 1574
15-67. 3-Phase Interleaved DC/DC Converter Waveforms for ........................................................... 1575
15-68. Controlling a Full-H Bridge Stage (F
PWM2
= F
PWM1)
.................................................................. 1578
15-69. ZVS Full-H Bridge Waveforms........................................................................................ 1579
15-70. Time-Base Control Register (TBCTL) ............................................................................... 1582
15-71. Time-Base Status Register (TBSTS) ................................................................................ 1584
15-72. Time-Base Phase Register (TBPHS) ................................................................................ 1584
15-73. Time-Base Counter Register (TBCNT) .............................................................................. 1585
15-74. Time-Base Period Register (TBPRD)................................................................................ 1586
15-75. Counter-Compare Control Register (CMPCTL) .................................................................... 1587
37
SPRUH73H–October 2011–Revised April 2013 List of Figures
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