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14-229. C2_RX_IMAX Register............................................................................................... 1471
14-230. C2_TX_IMAX Register ............................................................................................... 1472
14-231. RGMII_CTL Register ................................................................................................. 1473
14-232. MDIO Version Register (MDIOVER)................................................................................ 1474
14-233. MDIO Control Register (MDIOCONTROL) ........................................................................ 1475
14-234. PHY Acknowledge Status Register (MDIOALIVE)................................................................ 1476
14-235. PHY Link Status Register (MDIOLINK) ............................................................................ 1476
14-236. MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW) ........................................... 1477
14-237. MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED) .................. 1477
14-238. MDIO User Command Complete Interrupt Register (Raw Value) (MDIOUSERINTRAW) .................. 1478
14-239. MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED) ......... 1478
14-240. MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET) ............... 1479
14-241. MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR)............. 1480
14-242. MDIO User Access Register 0 (MDIOUSERACCESS0)......................................................... 1481
14-243. MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0).................................................... 1482
14-244. MDIO User Access Register 1 (MDIOUSERACCESS1)......................................................... 1483
14-245. MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1).................................................... 1484
15-1. PWMSS Integration .................................................................................................... 1488
15-2. IDVER Register......................................................................................................... 1490
15-3. SYSCONFIG Register ................................................................................................. 1491
15-4. CLKCONFIG Register ................................................................................................. 1492
15-5. CLKSTATUS Register ................................................................................................. 1493
15-6. Multiple ePWM Modules............................................................................................... 1495
15-7. Submodules and Signal Connections for an ePWM Module ..................................................... 1496
15-8. ePWM Submodules and Critical Internal Signal Interconnects................................................... 1497
15-9. Time-Base Submodule Block Diagram .............................................................................. 1501
15-10. Time-Base Submodule Signals and Registers ..................................................................... 1503
15-11. Time-Base Frequency and Period ................................................................................... 1505
15-12. Time-Base Counter Synchronization Scheme 1 ................................................................... 1506
15-13. Time-Base Up-Count Mode Waveforms............................................................................. 1508
15-14. Time-Base Down-Count Mode Waveforms ......................................................................... 1509
15-15. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event... 1509
15-16. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ...... 1510
15-17. Counter-Compare Submodule........................................................................................ 1511
15-18. Counter-Compare Submodule Signals and Registers............................................................. 1511
15-19. Counter-Compare Event Waveforms in Up-Count Mode ......................................................... 1514
15-20. Counter-Compare Events in Down-Count Mode ................................................................... 1514
15-21. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event ................................................................................................ 1515
15-22. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event .................................................................................................................... 1515
15-23. Action-Qualifier Submodule ........................................................................................... 1516
15-24. Action-Qualifier Submodule Inputs and Outputs ................................................................... 1517
15-25. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs......................................... 1518
15-26. Up-Down-Count Mode Symmetrical Waveform .................................................................... 1521
15-27. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................ 1522
15-28. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low................................................................................................. 1524
15-29. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA .......... 1526
36
List of Figures SPRUH73H–October 2011–Revised April 2013
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