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16-1. USB Integration......................................................................................................... 1694
16-2. USB GPIO Integration ................................................................................................. 1696
16-3. CPU Actions at Transfer Phases..................................................................................... 1704
16-4. Sequence of Transfer.................................................................................................. 1705
16-5. Flow Chart of Setup Stage of a Control Transfer in Peripheral Mode........................................... 1707
16-6. Flow Chart of Transmit Data Stage of a Control Transfer in Peripheral Mode................................. 1708
16-7. Flow Chart of Receive Data Stage of a Control Transfer in Peripheral Mode.................................. 1709
16-8. Flow Chart of Setup Stage of a Control Transfer in Host Mode.................................................. 1720
16-9. Flow Chart of Data Stage (IN Data Phase) of a Control Transfer in Host Mode............................... 1721
16-10. Flow Chart of Data Stage (OUT Data Phase) of a Control Transfer in Host Mode............................ 1723
16-11. Flow Chart of Status Stage of Zero Data Request or Write Request of a Control Transfer in Host Mode . 1724
16-12. Chart of Status Stage of a Read Request of a Control Transfer in Host Mode................................ 1726
16-13. Packet Descriptor Layout.............................................................................................. 1736
16-14. Buffer Descriptor (BD) Layout ........................................................................................ 1739
16-15. Teardown Descriptor Layout.......................................................................................... 1741
16-16. Relationship Between Memory Regions and Linking RAM ....................................................... 1746
16-17. High-level Transmit and Receive Data Transfer Example ........................................................ 1751
16-18. Transmit Descriptors and Queue Status Configuration ........................................................... 1753
16-19. Transmit USB Data Flow Example (Initialization) .................................................................. 1754
16-20. Receive Buffer Descriptors and Queue Status Configuration .................................................... 1756
16-21. Receive USB Data Flow Example (Initialization)................................................................... 1757
16-22. REVREG Register...................................................................................................... 1762
16-23. SYSCONFIG Register ................................................................................................. 1763
16-24. IRQSTATRAW Register ............................................................................................... 1764
16-25. IRQSTAT Register ..................................................................................................... 1765
16-26. IRQENABLER Register................................................................................................ 1766
16-27. IRQCLEARR Register ................................................................................................. 1767
16-28. IRQDMATHOLDTX00 Register....................................................................................... 1768
16-29. IRQDMATHOLDTX01 Register....................................................................................... 1769
16-30. IRQDMATHOLDTX02 Register....................................................................................... 1770
16-31. IRQDMATHOLDTX03 Register....................................................................................... 1771
16-32. IRQDMATHOLDRX00 Register ...................................................................................... 1772
16-33. IRQDMATHOLDRX01 Register ...................................................................................... 1773
16-34. IRQDMATHOLDRX02 Register ...................................................................................... 1774
16-35. IRQDMATHOLDRX03 Register ...................................................................................... 1775
16-36. IRQDMATHOLDTX10 Register....................................................................................... 1776
16-37. IRQDMATHOLDTX11 Register....................................................................................... 1777
16-38. IRQDMATHOLDTX12 Register....................................................................................... 1778
16-39. IRQDMATHOLDTX13 Register....................................................................................... 1779
16-40. IRQDMATHOLDRX10 Register ...................................................................................... 1780
16-41. IRQDMATHOLDRX11 Register ...................................................................................... 1781
16-42. IRQDMATHOLDRX12 Register ...................................................................................... 1782
16-43. IRQDMATHOLDRX13 Register ...................................................................................... 1783
16-44. IRQDMAENABLE0 Register .......................................................................................... 1784
16-45. IRQDMAENABLE1 Register .......................................................................................... 1785
16-46. IRQFRAMETHOLDTX00 Register ................................................................................... 1786
16-47. IRQFRAMETHOLDTX01 Register ................................................................................... 1787
16-48. IRQFRAMETHOLDTX02 Register ................................................................................... 1788
16-49. IRQFRAMETHOLDTX03 Register ................................................................................... 1789
40
List of Figures SPRUH73H–October 2011–Revised April 2013
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