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22-6. McASP Interface Signals .............................................................................................. 3787
22-7. Channel Status and User Data for Each DIT Block................................................................ 3794
22-8. Transmit Bitstream Data Alignment .................................................................................. 3805
22-9. Receive Bitstream Data Alignment................................................................................... 3807
22-10. McASP Registers Accessed Through Configuration Bus ......................................................... 3826
22-11. McASP AFIFO Registers Accessed Through Peripheral Configuration Port ................................... 3827
22-12. Revision Identification Register (REV) Field Descriptions ........................................................ 3828
22-13. Power Idle SYSCONFIG Register (PWRIDLESYSCONFIG) Field Descriptions............................... 3829
22-14. Pin Function Register (PFUNC) Field Descriptions................................................................ 3831
22-15. Pin Direction Register (PDIR) Field Descriptions .................................................................. 3833
22-16. Pin Data Output Register (PDOUT) Field Descriptions ........................................................... 3835
22-17. Pin Data Input Register (PDIN) Field Descriptions................................................................. 3837
22-18. Pin Data Set Register (PDSET) Field Descriptions................................................................ 3839
22-19. Pin Data Clear Register (PDCLR) Field Descriptions ............................................................. 3841
22-20. Global Control Register (GBLCTL) Field Descriptions ............................................................ 3842
22-21. Audio Mute Control Register (AMUTE) Field Descriptions........................................................ 3844
22-22. Digital Loopback Control Register (DLBCTL) Field Descriptions ................................................ 3846
22-23. Digital Mode Control Register (DITCTL) Field Descriptions ...................................................... 3847
22-24. Receiver Global Control Register (RGBLCTL) Field Descriptions ............................................... 3848
22-25. Receive Format Unit Bit Mask Register (RMASK) Field Descriptions........................................... 3849
22-26. Receive Bit Stream Format Register (RFMT) Field Descriptions ................................................ 3850
22-27. Receive Frame Sync Control Register (AFSRCTL) Field Descriptions ......................................... 3852
22-28. Receive Clock Control Register (ACLKRCTL) Field Descriptions ............................................... 3853
22-29. Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ......................... 3854
22-30. Receive TDM Time Slot Register (RTDM) Field Descriptions.................................................... 3855
22-31. Receiver Interrupt Control Register (RINTCTL) Field Descriptions.............................................. 3856
22-32. Receiver Status Register (RSTAT) Field Descriptions ............................................................ 3857
22-33. Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions ....................................... 3858
22-34. Receive Clock Check Control Register (RCLKCHK) Field Descriptions ........................................ 3859
22-35. Receiver DMA Event Control Register (REVTCTL) Field Descriptions ......................................... 3860
22-36. Transmitter Global Control Register (XGBLCTL) Field Descriptions ............................................ 3861
22-37. Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions .......................................... 3862
22-38. Transmit Bit Stream Format Register (XFMT) Field Descriptions................................................ 3863
22-39. Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions......................................... 3865
22-40. Transmit Clock Control Register (ACLKXCTL) Field Descriptions............................................... 3866
22-41. Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions......................... 3867
22-42. Transmit TDM Time Slot Register (XTDM) Field Descriptions ................................................... 3868
22-43. Transmitter Interrupt Control Register (XINTCTL) Field Descriptions........................................... 3869
22-44. Transmitter Status Register (XSTAT) Field Descriptions ......................................................... 3870
22-45. Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions ........................................ 3871
22-46. Transmit Clock Check Control Register (XCLKCHK) Field Descriptions ....................................... 3872
22-47. Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions ...................................... 3873
22-48. Serializer Control Registers (SRCTLn) Field Descriptions........................................................ 3874
22-49. Write FIFO Control Register (WFIFOCTL) Field Descriptions.................................................... 3877
22-50. Write FIFO Status Register (WFIFOSTS) Field Descriptions..................................................... 3878
22-51. Read FIFO Control Register (RFIFOCTL) Field Descriptions .................................................... 3879
22-52. Read FIFO Status Register (RFIFOSTS) Field Descriptions ..................................................... 3880
22-53. McASP Registers Accessed Through Data Port ................................................................... 3880
23-1. DCAN Connectivity Attributes......................................................................................... 3883
144
List of Tables SPRUH73H–October 2011–Revised April 2013
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